A current limiting technique is a very important protection technique of an inverter, which can effectively protect power switch elements when the inverter suddenly is heavily loaded or has a short-circuited output, so as to improve the impact resistance of the inverter. FIG. 1 shows a bridge arm output circuit diagram of a typical I-type three-level inverter. As shown in FIG. 1, the I-type three-level inverter comprises four switch transistors, i.e., a main switch transistor Q1 and an auxiliary switch transistor Q2 which are located at an upper bridge arm, and a main switch transistor Q4 and an auxiliary switch transistor Q3 which are located at a lower bridge arm.
At the time of a current limiting blockage, first, the main switch transistors Q1 and Q4 shall be turned off, and then the auxiliary switch transistors Q2 and Q3 shall be blocked after the main switch transistors Q1 and Q4 are reliably blocked. When an inductive current I drops to below a current protection threshold, a current limiting signal disappears, and after the current limiting signal disappears, an appropriate timing is selected to start de-blocking logic; that is, first, the two auxiliary switch transistors Q2 and Q3 are compulsorily turned on for a period of time, and after the auxiliary switch transistors Q2 and Q3 are reliably turned on such that a midpoint level is established, an auxiliary switch transistor (e.g. Q3) which is unnecessarily normally turned on is then turned off for a period of time and thereafter Q2 and Q3 are controlled to act according to normal switching logic, then the main switch transistors Q1 and Q4 are turned on, and the main switch transistors Q1 and Q4 are controlled to act according to normal switching logic, thereby ending the current limiting process and entering normal wave generation logic. The appropriate timing indicated herein refers to: when the current limiting signal disappears, whether the de-blocking logic is started immediately or the de-blocking logic is not started until an effective edge of PWM arrives. Generally speaking, wave-by-wave current limiting refers to that after the current limiting signal disappears, the de-blocking logic is not started until an effective edge of PWM arrives. For MOSFETs or IGBTs with an enough switching speed, it is also possible to enter the de-blocking logic once it is confirmed that the current limiting signal disappears, without waiting for an effective edge of PWM, and this current limiting manner is referred to as non-wave-by-wave current limiting manner.
However, in the existing current limiting techniques, the wave-by-wave current limiting manner has defects in regard to poor output voltage waveforms and in regard to mutual irrigation of energy between positive and negative buses; and although the non-wave-by-wave current limiting manner has better output voltage waveforms, it possibly involves more severe mutual irrigation of energy between positive and negative buses, resulting in a big risk of occurrence of an overvoltage to a unilateral bus, thus increasing a risk of damaging switch transistors.
To remove the defects in the aforementioned technical solutions, there is proposed an improved solution: the wave-by-wave current limiting manner is adopted for the main switch transistors, and the non-wave-by-wave current limiting manner allowing multiple times of turn-ons within one PWM cycle is adopted for the auxiliary switch transistors, so as to turn on the auxiliary switch transistors once the current limiting signal disappears, letting a bridge arm output voltage be at an N-line level. However, this solution still has the following significant disadvantage: after occurrence of the wave-by-wave current limiting, switching of the auxiliary switch transistors is possibly performed multiple times within one switching cycle, which is equivalent to that a switching frequency of the auxiliary switch transistors is n-times multiplied, which will greatly increase switching loss of diodes of the auxiliary switch transistors and the main switch transistors.